module top(clock,rst,dig[2:0],seg[7:0],key_in[2:0]);
input clock,rst;
input [2:0] key_in;
output [2:0] dig;
output [7:0] seg;
wire [23:0] out;
wire [23:0] date;
wire [2:0] key_out;
wire clk_out1,clk_out2,clk_out3,key_s;
div1 u1(clock,rst,clk_out1);
div2 u2(clock,rst,clk_out2);
counter u3(rst,clk_out1,out[23:0],date[23:0],key_out[2:0]);
smg3 u4(rst,clk_out2,out[23:0],date[23:0],dig[2:0],seg[7:0],key_s);
div3 u5(clock,rst,clk_out3);
xd u6(clk_out3,key_out[2:0],key_in[2:0],key_s);
endmodule
